IQ-DPHY-Tx is a MIPI D-Phy transmit physical layer IP core for Intel FPGA devices. It is designed to work with protocol engines utilizing the PPI interface for accessing the MIPI D-PHY Bus.

MIPI D-PHY specification describes a source synchronous, high-speed, low-power physical layer for the connection of camera and display applications to a host processor. MIPI D-PHY interface is the foundation for MIPI CSI2 and DSI higher layer protocols.

IQ-DPHY-Tx IP core allows FPGA users the ability to transmit data according to MIPI DPHY specification. Communication with the DSI or CSI2 protocol layers is done using the PHY Protocol Interface (PPI) recommended by the MIPI Alliance.

Key feature Set

  • One clock lane and up to four data lanes
  • Unidirectional high-speed mode with data rate up to 900Mbps
  • Bidirectional low-power operation modes with data rate of 10 Mbps
  • PHY-Protocol Interface (PPI) for connection to DSI and CSI-2 protocol layers

Commercial applications

  • Camera interfaces
  • Embedded displays
  • Automotive infotainment
  • Drones/UAVs
  • Industrial
  • Medical

Feature List

 

  • One clock lane and up to four data lanes
  • Unidirectional high-speed mode with data rate up to 900 Mbps
  • Bidirectional low-power operation modes with data rate of 10 Mbps
  • Ultra low-power mode (ULPS) and high-speed mode for clock lane
  • Ultra-low power mode, high-speed mode and escape mode support for data lanes
  • PHY-Protocol Interface (PPI) for connection to DSI and CSI-2 protocol layers
  • Compliant to MIPI Alliance Specification for D-PHY v1.0.0

 

Block Diagram

DPHY TX

 

Implementation Intel

 

FPGA family
LE REG
M9K IO Pins
MAX 10  667 565 0 20

IQ-DPHY-Tx Datasheet
  • Created: 2017-09-07
  •   Size: 421.54 KB
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