IQ-GraphBlit is a light-weight, high-performance 2D graphic accelerator IP core.
It comes with support for fast bitmap copy, conversion, solid fill and ROP operations, enhanced with Porter-Duff alpha blending and alpha masking.
Coupled with a comprehensive software and driver package, the IQ-GraphBlit is a powerful solution for high performance embedded graphics. IQ-Graphblit performs fast bitmap copy operations with support for ROP2 raster logical operations, solid fills, pattern generation and color depth conversion.
The blitting engine also supports Porter-Duff alpha blending operations allowing compositing of semitransparent images to obtain advanced rendering effects.
Alpha masking support allows for operations such as font texturing and image clipping.
The core is accompanied with a comprehensive driver and API suite supporting the entire core functionality, and allowing also accelerated rendering of graphic primitives such as lines and rectangles.
It integrates easily with Altera’s SOPC builder tools, or Lattice's IPexpress tools.
Commercial applications
- Vending machines
- Video monitors
- Automotive infotainment
- Medical instrumentation
Feature List
Supported graphical operations
- Raster image move and copy
- ROP2 binary raster operations
- 16 ROP2 operations
- Alpha blending operations
- 4 basic Porter-Duff alpha blending operations
- Alpha masking of RGB bitmaps
- Versatile pattern fill operations
- Solid color fill
- Color-key transparency
- Color depth conversion from any to any RGB format
Additional capabilities
- Configurable memory access
- 2 dedicated source pointers and 1 destination pointer
- Fully configurable copy source and destination addresses
- Source and destination bitmap resolutions up to 131071x131071
- Bitmap stripe size fully configurable
- Extensive pixel format support:
- 8-bit RGB (3:3:2)
- 16-bit RGB (5:6:5)
- 24-bit RGB/BGR
- 32-bit ARGB/ABGR
- 8-bit alpha bitmasks
- Available interrupt output
- Integrated DMA memory master supporting low-overhead burst transfers
- Configuration bus slave interface with address-mapped registers
- Comprehensive driver support
- Graphic primitives rendering
Block Diagram
Implementation - Altera
| FPGA family Cyclone III (EP3C10F484C6) |
LEs |
BRAMs (M9Ks) |
Multip. | Max. Freq. | IO Pins |
|
| Basic version (No alpha blending) |
2838 | 2 | 0 | 143 MHz * | 195 ** | |
| Full version (Alpha blending included) |
3233 | 2 | 4 | 137 MHz * | 195** | |
Implementation - Lattice
| FPGA family ECP3 (ECP3-35EA) |
LUT4s | Regs |
EBRs | Multip. | Max. Freq. | IO Pins |
| Basic version (No alpha blending) |
2630 | 1381 | 2 | 0 | 199 MHz * | 195 ** |
| Full version (Alpha blending included) |
2981 | 1526 | 2 | 4 | 183 MHz * | 195** |
| * |
Maximum frequency of the system bus interface, for AMBA AHB | |
| ** |
Assuming all core ports routed off-chip |
Feature highlights
Basic rendering operations
The core allows basic rendering applications such as image copy, solid color fill and text rendering.
ROP2 operations allow for rendering of sprites over image backgrounds, such as Windows icons.
The configurable memory interface, supporting two independent source pointers and a destination pointer with configurable stripe and color depth, allows efficient memory use and organization.
Alpha blending
Alpha blending allows the rendering of high quality antialiased graphical elements and images by allowing edge antialiasing through semitransparent pixels.
Advanced image compositing and combining is supported through Porter-Duff alpha blending operations, allowing for blending, clipping, overlaying, exclusion and other graphic effects.
Font texturing
Alpha blending operations in conjunction with alpha masking enables high quality type and font rendering with antialiased edges employing an alpha mask to render fonts.
An alpha mask can be generated by a standard, open source type rendering library such as FreeType, which allows rendering of TrueType and OpenType fonts.
Verification
The core has been rigorously tested in functional simulation and actual hardware.
The core is accompanied with an automated testbench with a system bus master simulation model and a system bus slave simulation model.
This core is marked as "AMPPSM Approved" and "SOPC Builder Ready".
The "AMPPSM Approved" mark indicates that this core meets Altera's sales standards and that this core has passed rigorous engineering testing.
The "SOPC Builder Ready" mark indicates that this core features plug-and-play integration with Altera's SOPC builder and the Nios® II processor over the Avalon® system interconnect.
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