IQ-LinkSPI is a frame-based wrapper for the SPI interface.
It is designed to receive frames containing commands for the bus operations and the wrapper configuration.
The IQ-link protocol is frame-based and supports error detection (complete frame error protection is guaranteed by a 16-bit CRC (CCITT)) and recovery.
The operations are issued by using an open, well documented protocol. By utilizing the IQ-Link protocol, an external master can control internal peripherals in a SoC.
LinkSPI doesn’t check for the compatibility with the system bus, so the SPI master will send only commands which conform to the bus specification.
Commercial applications
- Vending machines
- Video monitors
- Human machine interface (HMI) systems
- Industrial control and monitoring
Feature List
- Configurable SPI mode of operation and chip select polarity
- Mode 0 (CPOL=0, CPHA=0)
- Mode 1 (CPOL=0, CPHA=1)
- Mode 2 (CPOL=1, CPHA=0)
- Mode 3 (CPOL=1, CPHA=1)
- Detection of errors using a 16-bit CRC (CCITT)
- Decoupled command and response interfaces, allowing for high efficiency of the communication
- FIFO-based interface with configurable depth, allowing a trade-off between resource use and maximum number of commands issued before receiving responses
- Easy adaptation to the various FPGAs and various design requirements (ranging from slow, low-budget interfaces to the high bandwidth applications)
- Integrated DMA memory master supporting low-overhead burst transfers
- Master bus interfaces
- AMBA AHB
- AMBA AXI4
- Avalon®
- Peregrine*
Block Diagram
Implementation
Altera
| FPGA | LEs | BRAMs (M9Ks) | Multip. | Max. Freq. | IO |
| Cyclone III (EP3C16) | 892 | 2 | 0 | 162 MHz * | 119** |
Lattice
| FPGA | LUT4 | REG | EBR | Multip. | Max. Freq. | IO |
| ECP3 (LFE3-35EA) | 931 | 427 | 2 | 0 | 175 MHz * | 119** |
| * |
Maximum frequency of the system bus interface, for AMBA AHB | |
| ** |
assuming all core ports routed off-chip |
Verification
The core has been rigorously tested in functional simulation and actual hardware.
It is accompanied with an automated testbench with an SPI master simulation model and memory simulation model.
The memory model can be initialized with the desired data using the standard memory initialization file.
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