IQ-LinkUART is a frame-based wrapper for the UART interface.
It is designed to receive frames containing commands for the bus operations and the wrapper configuration.
Commercial applications
- Vending machines
- Video monitors
- Human machine interface (HMI) systems
- Industrial control and monitoring
Feature List
- Configurable UART bitrate (all standard and non-standard bitrates supported)
- Detection of errors using a 16-bit CRC (CCITT)
- Decoupled command and response interfaces, allowing for high efficiency of the communication
- FIFO-based interface with configurable depth, allowing a trade-off between resource use and maximum number of commands issued before receiving responses
- Easy adaptation to the various FPGAs and various design requirements (ranging from slow, low-budget interfaces to the high bandwidth applications)
- Integrated DMA memory master supporting low-overhead burst transfers
- Master bus interfaces
- AMBA AHB
- AMBA AXI4
- Avalon®
- Peregrine*
- Master bus interfaces
Block Diagram
Implementation
Altera
FPGA | LEs | BRAMs (M9Ks) | Multip. | Max. Freq. | IO |
Cyclone III (EP3C16) | 956 | 2 | 0 | 169 MHz * | 118** |
Lattice
FPGA | LUT4 | REG | EBR | Multip. | Max. Freq. | IO |
ECP3 (ECP3-35EA) | 963 | 449 | 2 | 0 | 174 MHz * | 118** |
* |
Maximum frequency of the system bus interface, for AMBA AHB | |
** |
assuming all core ports routed off-chip |
Verification
The core has been rigorously tested in functional simulation and actual hardware.
It is accompanied with an automated testbench with an SPI master simulation model and memory simulation model.
The memory model can be initialized with the desired data using the standard memory initialization file.
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