IQ-Mem | Memory Controller

IQ-Mem Memory controller is a low-cost modular memory controller for DDR/DDR2 SDRAM memories. It is designed to offer memory access to the system bus masters with maximum efficiency and minimum resource consumption.

Commercial applications

  • Vending machines
  • Video monitors
  • Automotive infotainment
  • Medical instrumentation
  • Human machine interface (HMI) systems
  • Mobile devices

Feature List

 

  • Configurable memory architecture (address width, data width, number of memory chips)
  • Configurable timing parameters and CAS latency (at core compile time)
  • Support for DDR and DDR2 SDRAM memories
  • Pre-configured proven timing setups for various memory vendors
  • Option for powering down external memory (auto-refresh mode) to lower power consumption
  • Option for avoiding the PRECHARGE command to keep banks open and reduce access latency
  • High-throughput design
  • Slave bus interfaces
    • AMBA AHB
    • AMBA AXI4
    • Avalon®
    • Peregrine*
    * Peregrine bus is Mikroprojekt's proprietary bus, optimized for FPGA architecture

Block Diagram

 

 

Implementation

 

Altera

FPGA LEs BRAMs (M9Ks) Multip. Max. Freq. IO
Cyclone III (EP3C16)  2184 3 0 158 MHz * 160**

 

Lattice

FPGA LUT4 Reg EBR Multip. Max. Freq. IO
ECP3 (LFE3-35EA)  526 497 0 0 215 MHz * 160**
*
  Maximum frequency of the system bus interface, for AMBA AHB
**
  assuming all core ports routed off-chip



Verification

 

The core has been rigorously tested in functional simulation and actual hardware.

IQ-Mem Data Sheet HOT
  • Created: 2015-05-15
  •   Size: 236.88 KB
  • Download



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