IQ-ScalR is a high performance video scaler, designed to support high-performance applications, with resolutions larger than full HD 1080p (up to 2048x2048).
The scaler is implemented as a pipeline structure accepting streaming video data which is driven frame by frame, pixel by pixel into the scaler structure in sync with the video control signals (vertical sync, horizontal sync, and data valid). The scaler generates and outputs the new (scaled) video frame data and the accompanying control signals.
Both upscaling and downscaling operations are supported. The scaling is performed by applying polyphase filtering to the input frame.
The number of filter taps and phases is programmable, allowing the fine tuning of the scaler size vs. the output quality.
The scaling ratios for X and Y axes are independent, allowing the image to be stretched or contracted if required. Scaling ratios can be changed for each frame, allowing scaling transitions and animated effects on video data.
The maximum and minimum scaling ratios for upscaling and downscaling are limited by the actual scaler implementation settings.
Commercial applications
- Digital signage
- Video monitors
- Video processors
- TVs, Set-Top Boxes
- Automotive infotainment
- Medical instrumentation
- Visualization systems
- Human machine interface (HMI) systems
Feature List
- Support for input and output resolutions up to 2048x2048
- Upscaling and downscaling with polyphase filtering
- Downscaling limited by the scaling ratio resolution
- Upscaling limited only by the ratio between the input pixel frequency (defined by the video source) and the scaler clock frequency
- Sync signal generation for output data
- Support for YUV or RGB color input
- Frame by frame image scaling
- Independent scaling factors for X and Y axes.
- Separation of the input pixel clock and the output pixel clock
- High-throughput design with deep pixel buffers
- Configurable scaling factor resolution
- Configurable number of filter taps
- Configurable width of the scaler interpolation filter data.
Block Diagram
Implementation Lattice
| FPGA family | LUT4s | Regs. |
EBRs | Multip. | Max. Freq. | IO Pins |
| ECP3 (ECP3-35EA) | 1145 | 1416 | 17 | 24 | 167 MHz * | 85 ** |
| * |
Maximum frequency of the system bus interface, for AMBA AHB | |
| ** |
Assuming all core ports routed off-chip |
Verification
The core has been rigorously tested in functional simulation and actual hardware.
The core is accompanied with an automated testbench with an image source simulation model and an image sink simulation model.
The image sink model can dump the received content to a file, allowing analysis of the simulation results through simple software provided with the model.
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