IQ-VIN is a high performance video input, designed for high-performance applications, supporting resolutions larger than full HD (up to 2048x2048) and stable operation in SoCs with limited memory bandwidth.
The IP Core accepts digital RGB or YUV video data, output from a HDMI 1.3/1.4a decoder, DisplayPort, HD-SDI, or other video reception interface.
IQ-VIN Integrates the IQ-ScalR video scaler IP, enabling frame-by-frame image scaling. Upscaling and downscaling are supported, independently for horizontal and vertical axis. Scaled images are outputted to memory in bursts with maximum efficiency.
Integrated image processing allows the color depth do be reduced from 24bpp pixels to 16bpp using dithering to achieve high image quality, while significantly reducing the required memory bandwidth.
The Bus architecture and scaler parameters are configurable at compile time, offering a trade-off between image quality/bus performance and resource consumption.
Commercial applications
- Digital signage
- Video monitors
- TVs, Set-Top Boxes
- Automotive infotainment
- Medical instrumentation
- Visualization systems
- Human machine interface (HMI) systems
Feature List
- Support for resolutions up to 2048x2048
- Support for RGB or YUV input
- Support for 16 or 24 bit RGB output color depth.
- Vertical and horizontal cropping of the input image.
- Dithering when reducing depth of the image from 24-bit on input to 16-bit in memory.
- Configurable width of the scaler interpolation filter.
- Frame by frame image scaling, independent scaling factors for X and Y axis.
- Complete separation of all clocks in the IP, allowing use of the fastest clocks only in scaler, and separate selection of the system bus clocks (set by the SoC requirements).
- Downscaling limited by scaler resolution, upscaling limited only by the ratio between input pixel frequency (defined by the video source) and scaler clock frequency (defined in the SoC)
- High-throughput design with deep pixel buffers, allowing for the robust stable behavior even on the busiest system buses.
- Frame sync output, frame skip support
- Integrated DMA memory master supporting low-overhead burst transfers
- Configuration bus slave interface with address-mapped registers
Block Diagram
Implementation Lattice
| FPGA family | Reg. | LUT4s |
EBRs | Multip. | Max. Freq. | IO Pins |
| ECP3 (ECP3-35EA) | 2807 | 2820 | 20 | 24 | 158 MHz * | 193 ** |
| * |
Maximum frequency of the system bus interface, for AMBA AHB | |
| ** |
Assuming all core ports routed off-chip |
Verification
The core has been rigorously tested in functional simulation and actual hardware.
The core is accompanied with an automated testbench with a display simulation model and a memory simulation model.
The memory model can be initialized with the desired bitmap through simple software provided with the model
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