IQ-DSI-Tx is a MIPI DSI protocol engine/transmitter IP core designed to work with PPI-compatible MIPI D-PHY serial interfaces for driving embedded displays.
MIPI DSI Transmitter IP core (IQ-DSI-Tx) together with DPHY-Tx IP core provides high speed serial interface between a host processor and a MIPI DSI-compliant display module.
MIPI DSI Transmitter converts a standard parallel video interface into DSI packets transferred to the physical layer (MIPI D-PHY) through the PHY Protocol Interface (PPI) recommended by the MIPI Alliance.
Key feature Set
- Clocked video interface at input
- PHY-Protocol Interface towards (PPI) D-PHY
- Supports DCS command transmission
- Data rate from 80 to 900 Mbps per lane
Commercial applications
- Camera interface
- Embedded displays
- Automotive infotainment
- ADAS systems
- Industrial
- Medical
Feature List
- Programmable number of serial data lanes (1-4)
- Data rate from 80 to 900 Mbps per lane
- PHY-Protocol Interface (PPI) towards D-PHY
- Clocked video interface at input
- HS (High Speed) mode transmission support
- Transmit and receive (bus turnaround) in LP (Low Power) mode
- Supports all DSI compatible video formats
- Video modes support (Non-burst with sync pulses, Non-burst with sync events, Burst mode)
- Register accessible command queue for transmission of command packets in HS Blank or LP mode
- Programmable EoTp generation
- ECC generation for header
- CRC generation for packet payload
- Avalon-MM interface for register access
- Compliant to MIPI Alliance Specification for Display Serial Interface v1.3.1
Block Diagram
Implementation Intel FPGA
| FPGA family | LE | REG |
M9K | IO Pins |
| MAX 10 | 1906 | 1167 | 34 | - |
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