IQ-CSI-Rx is a MIPI CSI-2 protocol engine/ receiver IP core designed to work with PPI-compatible MIPI D-PHY serial interfaces for capturing images from MIPI CSI-2 camera sensors..
MIPI CSI-2 Receiver IP core (IQ-CSI-Rx) together with the DPHY-Rx IP core provides the capability to receive MIPI CSI-2 compliant traffic from CSI camera sensors, and to decode received CSI packets as video data.
MIPI CSI-2 Receiver receives CSI packets from the MIPI D-PHY IP core through the PHY Protocol Interface (PPI) recommended by the MIPI Alliance. The received packets are then decoded and converted to the standard parallel video interface.
A couple of additional diagnostic capabilities are available to help with identifying the format of the incoming CSI stream. The IP core can be controlled over the Avalon-MM interface.
Key feature Set
- Clocked video interface at input
- PHY-Protocol Interface (PPI) towards D-PHY
- Data rate from 80 to 900 Mbps per lane
- Supports DCS command transmission
Commercial applications
- Camera interfaces
- Automotive infotainment
- Drones/UAVs
- Industrial
- Medical
Feature List
- Programmable number of serial data lanes (1-4)
- Data rate from 80 to 900 Mbps per lane
- PHY-Protocol Interface (PPI) towards D-PHY
- Clocked video interface at input
- HS (High Speed) mode receiving support
- Supports all primary video data formats (RAW, YUV, RGB)
- ECC generation for packet header
- CRC generation for packet payload
- Avalon-MM interface for register access
- Compliant to MIPI Alliance Specification for Camera Serial Interface v1.3.1
Block Diagram
Implementation Intel
| FPGA family |
LE | REG |
M9K | IO Pins |
| MAX 10 | 794 | 603 | 11 | N/A |
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