The IQ-DispLite is a lightweight, fully software configurable display controller IP core. It performs continuous refresh of graphical flat panel displays (TFT LCD, AMOLED) from a designated frame buffer located in a memory device mapped to the system bus.
It is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. All display settings (timing parameters, resolution, color depth) can be configured by software at run-time.
The IP core can be additionally scaled down at compile time by reducing bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispLite for a specific configuration.
Key feature Set
- Display and video interface driving
- Fully programmable
- Small footprint
- HD capable
- Vending machines
- Video monitors
- Automotive infotainment
- Medical instrumentation
- Human machine interface (HMI) systems
- Mobile devices
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096×4096
- Completely variable timing parameters, for standard or specific display resolutions
- Support for 8,16, 18 or 24 bit RGB output color depth
- Standard or multiplexed display data bus
- Display power control lines
- Interrupt generation on vertical sync for software synchronization
- Frame buffer management
- Double buffering to reduce image flicker
- Variable frame buffer organization with software-configurable memory stripe
- Image scroll via unconstrained frame buffer addressing
- Frame buffer color depth support
- Compile-time configuration for reducing resource cost by fixing parameters
- Support for multiple clock domains to ease timing closure
- Integrated DMA memory master supporting low-overhead burst transfers
- Configuration bus slave interface with address-mapped registers
|FPGA family||LEs||BRAMs (M9Ks)
||Multip.||Max. Freq.||IO Pins
|ECP3 (ECP3-35EA)||1316||3||0||154 MHz *||252 **|
||EBRs||Multip.||Max. Freq.||IO Pins
|ECP3 (ECP3-35EA)||952||1355||3||0||178 MHz *||252 **|
||Maximum frequency of the system bus interface, for AMBA AHB|
||Assuming all core ports routed off-chip|
The core has been rigorously tested in functional simulation and actual hardware. The core is accompanied with an automated testbench with a display simulation model and a memory simulation model.
The memory model can be initialized with the desired bitmap through simple software provided with the model.
This core is marked as “AMPPSM Approved” and “SOPC Builder Ready”.
The “AMPPSM Approved” mark indicates that this core meets Altera’s sales standards and that this core has passed rigorous engineering testing.
The “SOPC Builder Ready” mark indicates that this core features plug-and-play integration with Altera’s SOPC builder and the Nios® II processor over the Avalon® system interconnect.