MIPI CSI Solution

Deploy MIPI CSI Embedded Displays easily

The IQ-MIPI-CSI is a MIPI CSI-2 Interfacing solution for Intel FPGA devices. It enables reception and transmission of video data over the MIPI CSI-2 Interface on Intel MAX 10 FPGAs with the use of external passive D-Phy adapters.

Key feature Set

MIPI CSI-2 Transmit and Receive
High performance on Intel MAX 10
Highly configurable
Free IP Evaluation with OpenCore plus

Commercial applications

Automotive Infotainment/ADAS
Medical Displays
Home appliances
Digital Signage

The core uses a standard pixel interface consisting of a pixel clock, vertical and horizontal sync, blanking signal and data. The video and D-PHY timing and clock domains are completely decoupled for easier interfacing.

The D-PHY interface cores support passive resistor network implementations for transmit and receive with data rates up to 900 Mbps. The number of lanes is programmable and supports from 1 to 4 lanes.

Protocol engine blocks utilize the PPI interface as recommended by the MIPI specification to decouple the data layer from the PHYs. The Phy and Protocol IP Blocks integrate with the FPGA System through the Qsys tool. OpenCore Plus Evaluation is available on Intel FPGA platforms.

Programmable number of serial data lanes (1-4)
Supports passive D-PHY networks
Data rate from 80 to 900 Mbps per lane
PHY-Protocol Interface (PPI) between D-PHY and protocol engine
Standard parallel video interface at input/output
HS (High Speed) mode unidirectional communication

Bidirectional communication (bus turnaround) in LP (Low Power) mode
Wide range of pixel formats
Video modes support (burst, non burst with sync events, non burst with sync pulses)
Avalon-MM interface for register access and DCS command control
Compliant to MIPI Alliance Specification for Display Serial Interface v1.3.1

IQ-CSI-Rx

Programmable number of serial data lanes (1-4)
Data rate from 80 to 800 Mbps per lane
PHY-Protocol Interface (PPI) towards D-PHY
HS (High Speed) mode receiving support

IQ-CSI-Tx

Programmable number of serial data lanes (1-4)
Data rate from 80 to 900 Mbps per lane
PHY-Protocol Interface (PPI) towards D-PHY
HS (High Speed) mode transmission support

IQ-DPHY-Rx

One clock lane and up to four data lanes
Unidirectional high-speed mode with data rate up to 800 Mbps
Bidirectional low-power operation modes with data rate of 10 Mbps
Ultra low-power mode (ULPS) and high-speed mode for clock lane

IQ-DPHY-Tx

One clock lane and up to four data lanes
Unidirectional high-speed mode with data rate up to 900 Mbps
Bidirectional low-power operation modes with data rate of 10 Mbps
Ultra low-power mode (ULPS) and high-speed mode for clock lane

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