IQ-DSI-Rx is a MIPI DSI protocol engine/ receiver IP core designed to work with PPI-compatible MIPI D-PHY serial interfaces for driving embedded displays.

MIPI DSI Receiver IP core (IQ-DSI-Rx) together with the DPHY-Rx IP core provides the capability to receive MIPI DSI compliant traffic from a DSI host processor, and to decode received DSI video mode packets as video data.

MIPI DSI Receiver receives DSI packets from the MIPI D-PHY IP core through the PHY Protocol Interface (PPI) recommended by the MIPI Alliance. The received packets are then decoded and converted to the standard parallel video interface. A couple of additional diagnostic capabilities are available to help with identifying the format of the incoming DSI stream. The IP core can be controlled over the Avalon-MM interface.

Key feature Set

  • HS mode receive up to 800 MBps
  • PPI input 1-4 lanes
  • Clocked video interface at output
  • Supports all 24-bit, 18-bit and 16-bit DSI video formats

Commercial applications

  • Camera interfaces
  • Embedded displays
  • Automotive infotainment
  • ADAS systems
  • Industrial
  • Medical

Feature List

 

  • Programmable number of serial data lanes (1-4)
  • Data rate from 80 to 800 Mbps per lane
  • PHY-Protocol Interface (PPI) towards D-PHY
  • Clocked video interface at output
  • HS (High Speed) mode receiving support
  • Supports all 24-bit, 18-bit and 16-bit DSI compatible video formats
    • RGB888
    • RGB565
    • YCbCr
  • Video modes support (Non-burst with sync pulses, Non-burst with sync events)
  • ECC checking for header
  • CRC checking for packet payload
  • Avalon-MM interface for register access
  • Compliant to MIPI Alliance Specification for Display Serial Interface v1.3.1

 

Block Diagram

DSI RX

 

Implementation Intel

 

FPGA family LE REG
M9K IO Pins
MAX 10  3187 1406 5 -

IQ-DSI-Rx Datasheet
  • Created: 2017-09-07
  •   Size: 433.16 KB
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