MIPI DSI Solution

Deploy MIPI DSI Embedded Displays easily

 

 

The IQ-MIPI-DSI is a MIPI DSI Interfacing solution for Intel FPGA devices. It  enables reception and transmission of video data over the MIPI DSI Interface on Intel MAX 10 FPGAs with the use of external passive D-Phy adapters.
 

Key feature Set

  • MIPI DSI Transmit and Receive
  • High performance on Intel MAX 10
  • Highly configurable
  • Free IP Evaluation with OpenCore plus

Commercial applications

  • Automotive Infotainment/ADAS
  • Medical Displays
  • Home appliances
  • Digital Signage

The core uses a standard pixel interface consisting of a pixel clock, vertical and horizontal sync, blanking signal and data. The video and D-PHY timing and clock domains are completely decoupled for easier interfacing.


The DSI Transmitter IP Core supports DCS command issuing during HS blank or low power states for control of the DSI device registers and display power up. In LP mode the core supports readback from the MIPI Device with Bus-turn-around (BTA). The commands are issues from a queue accessed over the Avalon-MM host interface.


The D-PHY interface cores support passive resistor network implementations for transmit and receive with data rates up to 900 Mbps. The number of lanes is programmable and supports from 1 to 4 lanes.


Protocol engine blocks utilize the PPI interface as recommended by the MIPI specification to decouple the data layer from the PHYs. The Phy and Protocol IP Blocks integrate with the FPGA System through the Qsys tool. OpenCore Plus Evaluation is available on Intel FPGA platforms.

 

  • Programmable number of serial data lanes (1-4)
  • Supports passive D-PHY networks
  • Data rate from 80 to 900 Mbps per lane
  • PHY-Protocol Interface (PPI) between D-PHY and protocol engine
  • Standard parallel video interface at input/output
  • HS (High Speed) mode unidirectional communication

  • Bidirectional communication (bus turnaround) in LP (Low Power) mode
  • Wide range of pixel formats (16-30-bit)
  • Video modes support (burst, non burst with sync events, non burst with sync pulses)
  • Avalon-MM interface for register access and DCS command control
  • Compliant to MIPI Alliance Specification for Display Serial Interface v1.3.1

 

IQ-DSI-Rx

  • Programmable number of serial data lanes (1-4)
  • Data rate from 80 to 800 Mbps per lane
  • PHY-Protocol Interface (PPI) towards D-PHY
  • HS (High Speed) mode receiving support

          Read more...

 

IQ-DSI-Tx

  • Programmable number of serial data lanes (1-4)
  • Data rate from 80 to 900 Mbps per lane
  • PHY-Protocol Interface (PPI) towards D-PHY
  • HS (High Speed) mode transmission support

          Read more...

 

IQ-DPHY-Rx

  • One clock lane and up to four data lanes
  • Unidirectional high-speed mode with data rate up to 800 Mbps
  • Bidirectional low-power operation modes with data rate of 10 Mbps
  • Ultra low-power mode (ULPS) and high-speed mode for clock lane

          Read more...

 

IQ-DPHY-Tx

  • One clock lane and up to four data lanes
  • Unidirectional high-speed mode with data rate up to 900 Mbps
  • Bidirectional low-power operation modes with data rate of 10 Mbps
  • Ultra low-power mode (ULPS) and high-speed mode for clock lane

          Read more...

 

  • Based on Intel 10M50 Evaluation Kit
  • 10.1'' WUXGA (1920x1200) Display running at 60 fps
  • 7'' Raspberry PI 800x480 Display available
  • 4x MIPI D-Phy Lanes running up to 900 Mbps
  • Passive MIPI D-PHY Implementation
  • HDMI 1.4a input card allows direct video input to display

    More info coming soon...





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